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了解你的敌人

创建于: 2014-09-01 16:55:41          

[Know Your Enemy]

你有没有听说过一些CCIE考生曾经苦诉说,考试的失败并不是在于他们自身的过失?

如果你刚刚开始备考CCIE,我敢打赌,你一定会听到过这种抱怨,而我相信他们的这些抱怨一定也在你在复习备考前困扰着你。

 

当然出现这种考试失利,情有可原。所以我想借此机会与大家探讨一些考试注意事项,以便将总结失利的考试的一些教训。

 

有些情况下考试失败确实不是考生的责任,但在大多数情况下,失败的原因可能由于低效或无效的应试策略。正如上一篇的文章专家思维中提到,时间管理和细节注重是考试中两个最难以应付、最隐性的考试难点...

 

假设你已经对考试有了万全的准备,而且对考试充满着信心,精通考纲中大部分的技术性考点。你知道自己不知道的内容并且知道哪里可以快速地找到可靠的相关信息。你可以以专家级的表现,在给定的时间内精准高效地完成技术考题。

 

有人可能会认为这样就一定可以通过考试了。因而将考试失败归因为考题用词模棱两可,考官未给予恰当的支持,测试环境(工作站,键盘,鼠标,软件工具,界面,设备等)不适应 ,室温不适或考场噪音,椅子不适,或其他任何不在考生能控制之内的其他状况。

 

当然,再次声明,我并不是说这些情况一定不会发生。但对于一些非技术性考试技巧,例如如何缓解考试压力、如何管理考试时间、掌控考试风险及处理考点细节等情况你有考虑或准备过吗?如果你想通过考试,这些非技术性的考试技巧能够帮助你建立一套高效的考试实战策略,值得你花点时间来研究。

 

就像准备任何项目一样,你需要将所有可能发生的事情都纳入到你的计划中,而不仅仅是单看一些纯技术考点,对吗?

 

到底考试是什么?

 

开发和评估任何考试的最基本准则是有效性,可靠性及公平性。

 

举个例子,射箭考试目的是要评估一个弓箭手击中目标的能力。该测试需要持续,可靠和公平地衡量射手的表现。如果在不同特殊的测试条件下(距离相似的目标,弓的,箭头的和目标的属性,环境,天气等),弓箭手的箭一直能击中中心点,那我们可以选择细化测量基准,如根据弓箭手的培训程度、文化或地理区域,年龄,性别等进行划分。

 

下一个基本的考试设计的考量就是考试分数的使用目的。我们的考试真的像入学考试一样,为了选拔考试分数排名最前的10的考生吗?或不管有多少考生通过了考试,我们的考试目的就是要区分合格或未合格的考生?

 

依然以弓箭手测试为例,考试的目的是给至少能在最低概率,如80%击中靶心的射手授予专家级认证。

 

如果考试目的在于区分合格或合格过的考生,那么考题需定义出弓箭手通过考试的最低表现,以明确专家级弓箭手所具备的能力。

 

有多种方法可以客观地定义这个最低标准,当然这不是这篇文章真正的目的,所以让我们回到CCIE R&S V5.0考试讨论上。

 

考试设计属性

 

众所周知,无论有多少考生参加考试,CCIE考试的目的在于甄别合格的和不合格的网络工程师,任何考生能够证明他的表现达到或超过考试的标准都将会获得一个唯一的CCIE认证编号,不管他的考试分数多么靠近或远离及格线。在CCIE工程师中没有好CCIE和差CCIE之分。这就是为什么无论考生的分数达到或超过及格线,在他的成绩报告中只字未提而仅有一个“passed”的字样。刚达标的考生与拿满分的考生获得的认证是完全一样的。

 

当然这是不是建立考试策略时需考虑的基本因素呢?当然我们并不能仅仅考虑这一项因素......

 

让我们来看看其他已公布的可以为我们建立一个有效的考试策略所用的考试设计属性吧!

 

CCIE R&S V5.0考试是由四个独立的测试模块所组成:笔试(WR),和三个实验室考试模块:troubleshooting (TS), diagnostic (DIAG) and configuration (CFG)。这些测试模块每个都有自己的一套设计属性,我们先不讨论每一个细节,下表展示了四个模块之间的明显对比。

 

[ExamModulesDesignAttributes]

 

让我们来弄清楚每个属性,以避免任何混淆。

 

考试结果目的:如以上所讨论的,这是这个考试模块的最终目标。所有四个模块只有合格/不合格两个结果,实验室考试还有附加约束。我建议考生应以通过考试为目标,而其非试图比其他考生获得更好的成绩,甚至是以取得满分为目标!如果想要获得认证,把自我满足感先放在一边,着眼于通过考试,而不是取得满分。

 

逻辑算分上的限制:这是指应用于计算分数的附加规定。笔试和实验室考试都有一个分数线(即及格线),而只有实验室考试在需要达到的最低分数这个限制。不仅实验考试总成绩必须达到或超过实验室考试的及格线,全部三个模块的分数也必须达到或超过各自的实验模块的最低分数线。因此,考生可弥补较弱的模块,如用CFG中的强项弥补弱势的TS能力。如果总分(所有三个模块的分数之和)达到或超过了实验室考试的及格线,再加上如果每个模块的分数达到或超过了该模块的最低分数,那么考生就是及格了。如果任何模块的分数没有达到它的最低分数,那么整个考试也是不合格的,无论考生在其它模块中取得多少分数。这一点超级重要的。

 

考生在考试开始时可以看到所有的实验考题:笔试不允许来回答题。只可以答下一题,不能返回上一题。因此,在开始的笔试考试时,考生将无法看到所有的题目。而在实验室模块考试时,所有的题目在任何实验室模块开始时就可见。因此,考生可以挑选考题并决定以什么顺序来答题。这也是常被忽视的另一重要的考试属性。

 

考生可以看到题目的得分值:事先知道哪些考题相对于其他考题的分值这对决定如何应对考题,先选择哪些考题来答是很重要的。即使某个考题的得分值与其题目的难度并不一致,但这将极有可能帮助你安排答题的先后次序。

 

考题的得分机会:在CCIE R&S V5.0考试模块的所有考题都是以两分法为准计分,考生的得分结果要么是满分(该题目的分数值)要么就是没有分(零分) 。没有多点计分的考题,取得一少部分的分值是不可能的。因此,为了获得该题目的分数,考生必须答对该考题的所有要求。如你只能答对一少部分的要求,你不会取得的任何分数。CCIE R&S V5.0的考试模块中没有题目是采用多点计分的方式来算分的。。

 

考试期间可访问设备的控制台:只有TSCFG模块有提供远程控制台访问权给已运行的设备。笔试和DIAG模块只提供参考文档(例如图片,文字或工具,如流量分析器)。

 

用于整个考试的拓扑数目:由于笔试和DIAG并不依靠运行的设备,每个项目可使用单独的网络拓扑结构。 TS模块和CFG模块在单一的情况下也一样会依赖于整个考试模块中的单一拓扑结构。

 

考题相互依存(考题X的答案取决于考题Y的答案):只有CFG模块中的考题是相互依存的。三层的结果建立在二层的结果之上,所以如果你的二层答题失败,三层的答案正确的可能性非常之小。当我们在设计CFG模块场景及题目要求时,故意设计了这个两个层之间自然依存的自然的技术现象。

但其他三个考试模块的题目是相互独立的。所以在其他模块中TS的第三题答案并不依赖于第二题的答案!

 

可能的解决方案:在笔试和DIAG模块的所有题目都只有一个可能的解决方案;因此,他们的分数是有确定性的,自动化的脚本是非常简单的。而另一方面,TS模块和CFG模块为达到某个结果- 在大部分的情况下- 可以用多种不同的方法来实现。我们面对的挑战是需要尽可能少使用命令行,并且在不违反任何规则或存在额外的限制的情况下找到一个有效的解决方案。

 

时间限制:我想不出任何考试中会不涉及到时间的掌握。所以很自然的,在我们的考试中有时间限制。然而,考虑到考试有一定的压力,CCIE R&S V5.0为实验考试引入了灵活性的时间限制。TS模块被设计为两小时内是可完成的内容,而考试系统允许考生使用两个半小时完成TS模块的题目。由于总考试时间仍限于八小时,这个项可额外选择的时间,自动会从CFG模块的考试时间中被抵扣掉。考生可选择是否向CFG模块借30分钟,并把它用在TS模块中。这是一个策略性的决定,考生应该在考试之前仔细考虑是否使用该选项。 DIAG模块的考试时间是固定的30分钟,不能多也不能少。所以没有弹性或策略性决策可做。

 

请记住,这些考试设计的特性都可能会发生变化,并且上表适用于当前的20148月的CCIE R&S V5.0考试。

 

在接下来的文章中,我将尝试编写一些具体的建议和一些关于考试设计属性的有效策略例子。

 

我希望这是有用的。你可像往常一样,随时在下面发表评论。

 


 

中英对照:

[Know Your Enemy]

Have you ever heard or read stories about CCIE candidates claiming that their failure at taking the test is not their fault?

If you’ve started your journey toward earning your CCIE number, I’ll bet you’ve heard or read these and, in turn, I’ll bet that these are important concerns to you as you prepare for the exam.

 

This is, of course, legitimate and I’d like to take a moment to discuss some considerations that might put these stories into perspective. While there are some instances where test failures are indeed not candidate’s responsibility, in most cases, failure actually comes down to ineffective or nonexistent test taking strategies. As discussed in the previous articles The Expert’s Mindset, time management and attention to the details are the two most vicious and implicit metrics of the exam

 

Let's assume that you have extensively and properly prepared for the exam and that you’re feeling confident and proficient with most technical topics in the exam curriculum. You know what you don’t know and you know where to quickly find reliable information about it. You are able to effectively and efficiently perform technical tasks at the expected performance level in terms of time, amount of work and technical accuracy.

 

One could think that this is all that it takes to pass the exam and therefore failure must be due to wording ambiguity, the test administrator’s lack of support, the test environment (workstation, keyboard, mouse, software tools, interface, devices, etc), the room temperature or background noise, the uncomfortable chair, or any other condition that is not in the candidate’s control.

 

Again, I'm not saying that these conditions never happened, but well, how about non-technical skills such as exam-taking skills, stress, time and risk management, attention to the detail, etc?

If you want to pass the exam, it might be worth spending some time to consciously build an effective strategy that accounts for all of these non-technical aspects.

 

Just like for any project, you will want to include all variables into the planning, not just the technical angle, right?

 

What Is an Exam?

The most fundamental considerations in developing and evaluating any test are its validity, reliability and fairness.

 

For instance, if a test were intended to endorse an archer's ability for hitting a target, the test would need to consistently, reliably and fairly measure the archer's performance. So if the archer's arrows are consistently hitting the center of the target, in identical test conditions (similar distance to the target, bow's, arrow's and target's attributes, environment, weather, etc), then we have minimized bias, such as the archer's training or culture or geographic region, age, gender, etc.

 

The next fundamental consideration in test development is the intended use of the test score. Is the test intended to rank candidates and select only the best 10 percent, like a college entrance test? Or is the test intended to discriminate between qualified and non-qualified candidates, regardless of how many candidates already passed it?

 

In this archer’s test example, the intended use of the test could be to grant an expert-level certificate to any archer who is able to reach the center of the target at a minimum rate of say 80 percent of arrows fired (among other tasks).

 

So if the intention is to make a pass or fail decision, then the test needs to define what is the minimum performance required of archers to pass the test in order to be recognized as an expert-level archer. There are multiple ways to objectively define this minimum performance level but it’s not really the purpose of this article so let’s focus back on our CCIE R&S v5.0. 

 

Exam Design Attributes

As you know, the intended use of the CCIE test is to discriminate between qualified and non-qualified engineers, regardless of how many candidates take or pass the test. Anyone who is able to demonstrate that his/her performances meet or exceed the test’s cut-score will receive a CCIE number, regardless of how close or how far his/her score is compared to the cut-score. There is no concept of better or worse CCIE. This is why the score report doesn’t mention anything other than passed when the candidate’s score meets or exceeds the cut-score. Someone who aces the exam with 100 percent receives the exact same credential as someone else who passes the exam on the borderline!

Isn't this a fundamental consideration when building a strategy to succeed on the exam?

And it's not the only one 

 

Let's see what other design attributes are publicly disclosed and which ones could be useful in building that effective strategy.

 

The CCIE R&S v5.0 exam is composed of four independent test modules: the written exam (WR), and the three lab exam modules: troubleshooting (TS), diagnostic (DIAG) and configuration (CFG). Each one of these test modules has its own set of design attributes and rather than discussing each one in detail, the following table provides a clear comparison between all four modules.

 

 [ExamModulesDesignAttributes]

Let's clarify each attribute to avoid any ambiguity.

 

Intended use of the test result: As discussed above, this is the final objective of the exam module. All four modules are pass/fail exams, with the additional constraints in the lab exam. I would suggest that a candidate should target passing the exam and avoid trying to get a better score than anyone else or even ace the exam! If needed, put the ego aside and aim at passing the exam, not acing it!

 

Constraints in scoring logic: This refers to the additional rules applied to the scoring calculation. Both the written and lab exams define a cut-score (that is, a passing score) while only the lab exam requires meeting the additional restriction of the minimum score. Not only does the total score need to meet or exceed the lab-level cut-score, but also all three modules’ score must meet or exceed their respective module-level minimum score. So a candidate may compensate for weakness in a module, like TS, with strength in CFG. If the total score (sum of all three modules’ score) meets or exceeds the lab-level cut-score and if each module’s score meets or exceeds its module-level minimum-score, then it is a pass. If any module’s score doesn’t meet its minimum-score, then the whole exam is failed, regardless of the score in other modules. This is super important.

 

All items are visible at the start of the exam: The written exam doesn’t allow going back and forth between questions (items). It is only possible to move forward, not backward. Therefore, a candidate will not see all items when starting the written exam. On the other hand, all items are available when starting any lab module. So a candidate can cherry pick items or decide on which sequence to address items. This is another important attribute that is frequently overlooked.

 

Item’s score value is visible during the exam: Knowing beforehand which item has more or less point value’ compared to others is also important when deciding how to approach the exam and which item to address first. Even though an item’s point doesn’t always indicate difficulty, it will most likely help to prioritize items relative to each other.

 

Item’s scoring opportunities: All items in the CCIE R&S v5.0 exam modules are dichotomous: their possible score outcome is either everything (the item’s score value) or nothing (zero points). There are no polytomous items, which would allow scoring only a portion of the item’s score value. So in order to get the item’s score value, a candidate must meet all requirements of the item. Meeting only a subset of the requirements doesn’t get you a portion of the score value. There is no partial grading in any exam module of CCIE R&S v5.0.

 

Access to devices’ console during the exam: Only the TS and CFG modules offer remote console access to living devices. The written exam and DIAG provide documentation only (pictures, text or eventually tools such as traffic analyzer).

 

Number of topologies used throughout the exam: Since the written exam and DIAG do not rely on living devices, each item may use a separate network topology. Both TS and CFG are based on a single scenario that relies on a single topology that is used throughout the exam module.

 

Items inter-dependence (resolution of item X depends on resolution of item Y): Only CFG’s items are inter-dependent. Layer 3 builds on top of Layer 2, so if your Layer 2 is broken, there is a small chance that Layer 3 will work as expected. This is the nature of the technologies that we’re dealing with and testing these inter-dependencies is intentional when designing CFG’s scenarios and item requirements. But the items of all three other exam modules are independent of each other. So the resolution of TS item number 3 doesn’t rely on the resolution of item number 2!

 

Possible solution(s): All items on the written exam and the DIAG module have only one possible solution; therefore their scoring is deterministic and the automated script is simple. On the other hand, TS and CFG items are expecting specific outcomes that most of the time can be achieved using many different approaches. The challenge is finding an efficient solution that requires as few command-line interactions as possible and not violate any guideline or additional constraint.

 

Time limit: I can’t think of any performance measurement that doesn’t involve time. So it is natural that performance tests have a time limit. However, with the pressure of the exam itself, CCIE R&S v5.0 introduces some flexibility in the lab exam. While TS is designed to be doable within two hours, the system allows candidates to spend up to two and a half hours working on TS items. Since the total exam time is still limited to eight hours, this optional additional time is then automatically deducted from the time credit allotted to CFG. It is the candidate’s choice whether to borrow up to thirty minutes from CFG and use it in TS. This is a strategic decision and candidates should consider carefully whether or not to use that option before taking the exam. DIAG’s time limit is fixed to thirty minutes, no more and no less. So there’s no flexibility or strategic decision there.

 

Please keep in mind that all these design attributes are subject to change and that the above table is applicable for the current CCIE R&S v5.0, as of August 2014.

 

In the next article, I'll attempt to compile some concrete recommendations and examples of efficient strategies that take into account these exam design attributes.

 

I hope this is useful. As usual, please feel free to comment below.

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